GW2A-LV18PG484C8/I7 GOWIN FPGA with 0.95V Core Voltage and JTAG Download in PBGA-484 Package

GW2A-LV18PG484C8/I7 PBGA-484 Programmable Logic Device Chip GOWIN

GW2A/GW2AR series of FPGA Products Schematic Manual

IntroductionUsers should follow a series of rules during circuit board design whenusing the GW2A/GW2AR series of FPGA products. This manual describesthe characteristics and special features of GW2A/GW2AR series FPGAproducts and provides a comprehensive checklist to guide designprocesses. The main contents of this guide are as follows:

• Power Supply
• JTAG download
• MSPI download
• Clock pin
• Difference pin
• READY, RECONFIG_N, DONE
• MODE
• JTAGSEL_N
• FASTRD_N
• EXTR
• Pin Multiplexing
• Reference for the external crystal oscillator circuit
• GW2AR Bank voltage
• Supported configuration modes
• Pin Distribution

Power Supply

1. Overview

Voltage types of the GW2A/GW2AR series of FPGA products includecore voltage (VCC), PLL voltage (VCCPLL), auxiliary voltage (VCCX) and Bankvoltage (VCCIO).VCCX is an auxiliary power supply that is used to connect the internalpart of the chip, with a 2.5V or 3.3V power supply. If no VCCX exists, I/O,OSC, and BSRAM circuits will be impacted and the chip will not befunctional.

2. Power Index

Users should ensure GOWINSEMI products are always used within recommended operating conditions and range. Data beyond the workingconditions and range are for reference only. GOWINSEMI does notguarantee that all devices will operate as expected beyond the standardoperating conditions and range.

Table 1 lists the recommended working range for each power voltage.

Table 2 Recommended Working Range

3. Total Power

For specific density, packages, and resource utilization, GPA tools canbe used to evaluate and analyze the power consumption.

4. Power-on time

Reference range of power-on time: 0.2 ms ~ 2 ms.

Note!

• If the power-on time is more than 2ms, you need to ensure that the power-on insequence is VCC, and then VCCX/VCCIO;
• If the power-on time is less than 0.2ms, it is recommended to increase thecapacitance to prolong the power-on time.

5. Power Filter

Each FPGA power input pin is connected to the ground with a 0.1uFceramic capacitor.The input end of the VCC core voltage should primarily conduct thenoise processing. Specific reference is as shown in Figure 1:

Figure 1 Noise Processing of the Input End of the VCC Core Voltage

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