18Mbit Static SRAM Chip 6.5 Ns COMS CY7C1381KV33-133AXI

• Supports 133 MHz bus operations
• 512K × 36 and 1M × 18 common I/O
• 3.3 V core power supply (VDD)
• 2.5 V or 3.3 V I/O supply (VDDQ)
• Fast clock-to-output time: 6.5 ns (133 MHz version)
• High performance 2-1-1-1 access rate
• User selectable burst counter supporting interleaved or linear burst sequences
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• ZZ sleep mode option
• On-chip error correction code (ECC) to reduce soft error rate (SER)

The CY7C1381KV33 series are 3.3 V, 512K × 36 and 1M × 18 synchronous flow through SRAMs designed to interface with high speed microprocessors with minimum glue logic. These devices feature a maximum access delay of 6.5 ns (133 MHz version) and include a 2-bit on-chip counter for burst address generation.

All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK). The devices operate from a +3.3 V core power supply while all outputs operate with a +2.5 V or +3.3 V supply. All inputs and outputs are JEDEC-standard and JESD8-5-compatible.

Standard export packaging available. Customers can choose from cartons, wooden cases and wooden pallets according to their requirements.