32MB 1.7V 2V PSRAM Chip 8 Bit TFBGA W958D8NBYA5I-TR Static Random Access Memory Chip

• Interface: HyperBus
• Power supply: 1.7V~2.0V
• Maximum clock rate: 250MHz
• Double-Data Rate (DDR) Up to 500 MB/s
• Operating temperature range: -40°C ≤ TCASE ≤ 85°C
• Configurable Burst Characteristics
• Array Refresh Modes
• 24 balls TFBGA package

The HyperBus interface achieves high speed read and write throughput with a low signal count, Double Data Rate (DDR) interface. The DDR protocol transfers two data bytes per clock cycle on the DQ input/output signals.

All inputs and outputs are LV-CMOS compatible. Command, address, and data information is transferred over the eight HyperBus DQ[7:0] signals. The clock (CK#, CK) is used for information capture by a HyperBus slave device.

Every transaction begins with the assertion of CS# and Command-Address (CA) signals, followed by the start of clock transitions to transfer six CA bytes, followed by initial access latency and either read or write data transfers.

Standard export packaging available. Customers can choose from cartons, wooden cases and wooden pallets according to their requirements.