DDR3 SDRAM Memory Chip IMD128M16R39CG8GNF-125

• VDD = VDDQ = 1.5V ±0.075V
• 1.5V center-terminated push/pull I/O
• Differential bidirectional data strobe
• 8n-bit prefetch architecture
• Differential clock inputs (CK, CK#)
• 8 internal banks
• Nominal and dynamic on-die termination (ODT)for data, strobe, and mask signals
• Programmable CAS READ latency (CL)
• Posted CAS additive latency (AL)
• Programmable CAS WRITE latency (CWL) based ontCK
• Fixed burst length (BL) of 8 and burst chop (BC) of 4(via the mode register set [MRS])
• Selectable BC4 or BL8 on-the-fly (OTF)
• Self refresh mode
• TC of 0°C to 70°C
• Self refresh temperature (SRT)
• Automatic self refresh (ASR)
• Write leveling
• Multipurpose register
• Output driver calibration

• 1. Marking
  • Configuration
    • 512 Meg x 4 512M4
    • 256 Meg x 8 256M8
    • 128 Meg x 16 128M16
  • FBGA package (Pb-free) – x4, x8
    • 78-ball (8mm x 10.5mm) Rev. K /
    • 78-ball (8mm x 10.5mm) Rev. N /
  • FBGA package (Pb-free) – x16
    • 96-ball (8mm x 14mm) Rev. K GNF
    • 96-ball (8mm x 14mm) Rev. N /
  • Timing – cycle time
    • 938ps @ CL = 14 (DDR3-2133) -093
    • 1.07ns @ CL = 13 (DDR3-1866) -107
    • 1.25ns @ CL = 11 (DDR3-1600) -125
    • 1.5ns @ CL = 9 (DDR3-1333) -15E
    • 1.87ns @ CL = 7 (DDR3-1066) -187E
  • Operating temperature
    • Commercial (0°C ≤ TC ≤ +70°C) None
    • Industrial (–40°C ≤ TC ≤ +95°C) IT
  • Revision :K / :N

Standard export packaging available. Customers can choose from cartons, wooden cases, and wooden pallets according to their requirements.