MT41K256M16TW-107 IT:P DRAM DDR3L Memory 4 Gbit 16 bit 933 MHz FBGA-96 Industrial Grade

• VDD = VDDQ = 1.35V (1.283–1.45V)
• Backward compatible to VDD = VDDQ = 1.5V ±0.075V
  • Supports DDR3L devices to be backward compatible in 1.5V applications
• Differential bidirectional data strobe
• 8n-bit prefetch architecture
• Differential clock inputs (CK, CK#)
• 8 internal banks
• Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
• Programmable CAS (READ) latency (CL)
• Programmable posted CAS additive latency (AL)
• Programmable CAS (WRITE) latency (CWL)
• Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS])
• Selectable BC4 or BL8 on-the-fly (OTF)
• Self refresh mode
• TC of 105°C
  • 64ms, 8192-cycle refresh up to 85°C
  • 32ms, 8192-cycle refresh at >85°C to 95°C
  • 16ms, 8192-cycle refresh at >95°C to 105°C
• Self refresh temperature (SRT)
• Automatic self refresh (ASR)
• Write leveling
• Multipurpose register
• Output driver calibration

• Configuration
  • 1 Gig x 4 1G4
  • 512 Meg x 8 512M8
  • 256 Meg x 16 256M16
• FBGA package (Pb-free) – x4, x8
  • 78-ball (9mm x 10.5mm) Rev. E RH
  • 78-ball (7.5mm x 10.6mm) Rev. N RG
  • 78-ball (8mm x 10.5mm) Rev. P DA
• FBGA package (Pb-free) – x16
  • 96-ball (9mm x 14mm) Rev. E HA
  • 96-ball (7.5mm x 13.5mm) Rev. N LY
  • 96-ball (8mm x 14mm) Rev. P TW
• Timing – cycle time
  • 938ps @ CL = 14 (DDR3-2133) -093
  • 1.07ns @ CL = 13 (DDR3-1866) -107
  • 1.25ns @ CL = 11 (DDR3-1600) -125
• Operating temperature
  • Commercial (0°C TC +95°C) None
  • Industrial (–40°C TC +95°C) IT
  • Automotive (–40°C TC +105°C) AT
• Revision :E/:N/:P

Standard export packaging available. Customers can choose from cartons, wooden cases, and wooden pallets according to their requirements.