PBGA-256 CPLD/FPGA Programmable Logic Device Chip GW2A-LV18PG256C8/I7
Product Specifications
| Attribute |
Value |
| (LUT4) |
20,736 |
| (FF) |
15,552 |
| SSRAM(bits) |
40K |
| BSRAM(bits) |
828K |
| BSRAM(个) |
46 |
| (18x18 Multiplier) |
48 |
| (PLLs) |
4 |
Product Description
The GW2A/GW2AR series FPGA products require adherence to specific design rules for circuit board implementation. This manual outlines the features and special functions of these FPGA products, providing a comprehensive checklist to guide the design process.
Key Design Considerations
- Power supply requirements
- JTAG download configuration
- MSPI download process
- Clock pin specifications
- Differential pin configurations
- READY, RECONFIG_N DONE signals
- Mode selection parameters
- JTAGSEL_N functionality
- FASTRD_N operation
- EXTR features
- Pin multiplexing options
- External crystal oscillator circuit references
- GW2AR Bank voltage specifications
- Supported configuration modes
Power Supply
The GW2A/GW2AR series FPGA products utilize multiple voltage types:
- Core voltage (VCC)
- PLL voltage (VCCPLL)
- Auxiliary voltage (VCCX)
- Bank Voltage (VCCIO)
VCCX serves as an auxiliary power supply for internal chip connections, typically requiring 2.5V or 3.3V. Without proper VCCX supply, I/O, OSC and BSRAM circuits will be affected, rendering the chip non-functional.
Power Specifications
Users must ensure operation within recommended working conditions. For power consumption analysis, the GPA tool can evaluate specific densities, encapsulation and resource utilization.
Power-on Timing
Recommended power-on time range: 0.2ms to 2ms.
Important: If power-on exceeds 2ms, ensure sequential power-on begins with VCC followed by VCCX/VCCIO. For power-on under 0.2ms, additional capacitors may be required to extend the duration.
Power Filtering
Each FPGA power input pin should connect to ground through a 0.1μF ceramic capacitor. VCC core voltage input requires specific noise processing.
JTAG Download
JTAG download enables bitstream data transfer to SRAM, on-chip flash or off-chip flash.
| Signal |
I/O |
Description |
| TCK |
I |
Serial clock input in JTAG mode |
| TMS |
I |
Serial mode input with weak internal pull-up in JTAG mode |
| TDI |
I |
Serial data input with weak internal pull-up in JTAG mode |
| TDO |
O |
Serial data output in JTAG mode |
Product Comparison
| Feature |
GW2A-18 |
GW2A-55 |
| (LUT4) |
20,736 |
54,720 |
| (FF) |
15,552 |
41,040 |
| SSRAM(bits) |
40K |
106K |
| BSRAM(bits) |
828K |
2,520K |
| BSRAM(个) |
46 |
140 |
| (18x18 Multiplier) |
48 |
40 |
| (PLLs) |
4 |
6 |
| I/O Bank |
8 |
8 |
| GPIO |
384 |
608 |
Packaging and Shipping
- Standard export packaging available
- Custom packaging options: cartons, wooden cases, wooden pallets
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