PLD SMD Mounting FPGA Field Programmable Gate Array EPM240T100C5N

The MAX® II family of instant-on, non-volatile CPLDs is based on a 0.18-µm, 6-layer metal-flash process, with densities from 240 to 2,210 logic elements (LEs) (128 to 2,210 equivalent macrocells) and non-volatile storage of 8 Kbits.

• Low-cost, low-power CPLD
• Instant-on, non-volatile architecture
• Standby current as low as 29 µA
• Fast propagation delay and clock-to-output times
• Four global clocks with two clocks available per logic array block (LAB)
• UFM block up to 8 Kbits for non-volatile storage
• MultiVolt core enabling external supply voltages of either 3.3 V/2.5 V or 1.8 V
• MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic levels
• Bus-friendly architecture including programmable slew rate, drive strength, bus hold, and programmable pull-up resistors
• Schmitt triggers enabling noise tolerant inputs (programmable per pin)
• I/Os fully compliant with PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 66 MHz
• Supports hot-socketing
• Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990
• ISP circuitry compliant with IEEE Std. 1532

According to the standard export packaging. Customers can choose from cartons, wooden cases and wooden pallets according to their own requirements.