DDR3 SDRAM Memory Chip 1GB 1.5V FBGA-96 8K Refresh IMD64M16R38AG8GNF

• VDD = VDDQ = +1.5V ±0.075V
• 1.5V center-terminated push/pull I/O
• Differential bidirectional data strobe
• 8n-bit prefetch architecture
• Differential clock inputs (CK, CK#)
• 8 internal banks
• Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
• CAS (READ) latency (CL): 5, 6, 7, 8, 9, 10, or 11
• POSTED CAS ADDITIVE latency (AL): 0, CL - 1, CL - 2
• CAS (WRITE) latency (CWL): 5, 6, 7, 8, based on tCK
• Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS])
• Selectable BC4 or BL8 on-the-fly (OTF)
• Self refresh mode
• TC of 0°C to 95°C
  • 64ms, 8,192 cycle refresh at 0°C to 85°C
  • 32ms at 85°C to 95°C
• Clock frequency range of 300–800 MHz
• Self refresh temperature (SRT)
• Automatic self refresh (ASR)
• Write leveling
• Multipurpose register
• Output driver calibration

• ICMAX Memory
• Configuration
  • 256 Meg x 4
  • 128 Meg x 8
  • 64 Meg x 16
• Product Code
  • DDR3
• Density
  • 1 Gigabyte
• Voltage/Refresh
  • 1.5V/8k refresh
• FBGA package (Pb-free) - x4, x8
  • 78-ball (8mm x 11.5mm) Rev. E, F
  • 78-ball (9mm x 11.5mm) Rev. D
  • 78-ball (8mm x 10.5mm) Rev. J
  • 86-ball (9mm x 15.5mm) Rev. B
• FBGA package (Pb-free) - x16
  • 96-ball (8mm x 14mm) Rev. E
• Timing - cycle time
  • 1.25ns @ CL = 11 (DDR3-1600)
  • 1.25ns @ CL = 10 (DDR3-1600)
  • 1.5ns @ CL = 10 (DDR3-1333)
  • 1.5ns @ CL = 9 (DDR3-1333)
  • 1.87ns @ CL = 8 (DDR3-1066)
  • 1.87ns @ CL = 7 (DDR3-1066)

IMD256M4128M864M16Dxx8G**G**Z**GNF-125-125E-15-15E-187-187E

Standard export packaging available. Customers can choose from cartons, wooden cases, and wooden pallets according to their requirements.