DDR3 4Gb SDRAM Memory Chip FBGA-96 8K Refresh IMD256M16R30HG8GNF-107

(TBD)1024M4 – 128 Meg x 4 x 8 Banks

(TBD)512M8 – 64 Meg x 8 x 8 Banks

(IMD256M16R30HG8GNF-125/107)256M16 – 32 Meg x 16 x 8Banks

• VDD = VDDQ = +1.5V ±0.075V
• 1.5V center-terminated push/pull I/O
• Differential bidirectional data strobe
• 8n-bit prefetch architecture
• Differential clock inputs (CK, CK#)
• 8 internal banks
• Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
• Programmable CAS (READ) latency (CL)
• Posted CAS Addictive latency (AL)
• Programmable CAS (WRITE) latency (CWL) based on tCK
• Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS])
• Selectable BC4 or BL8 on-the-fly (OTF)
• Self refresh mode
• TC of 0°C to 85°C
  • 64ms, 8,192 cycle refresh at 0°C to 85°C
  • 32ms, 8,192 cycle refresh at 85°C to 95°C
• Self refresh temperature (SRT)
• Write leveling
• Multipurpose register
• Output driver calibration

• ICMAX Memory
• Configuration
  • 1 Gig x 4
  • 512 Meg x 8
  • 256 Meg x 16
• Product Code
  • DDR3
• Density
  • 4 Gigabytes
• Voltage/Refresh
  • 1.5V/8k refresh
• FBGA package (Pb-free) - x4, x8
  • 78-ball (10.5mm x 12mm)
  • 78-ball (9mm x 10.5mm)
  • 78-ball (8mm x 10.5mm)
  • 78-ball (7.5mm x 10.6mm)
• FBGA package (Pb-free) - x16
  • 96-ball (10mm x 14mm)
  • 96-ball (8mm x 14mm)
• Timing - cycle time
  • 1.07ns @ CL = 13 (DDR3-1866)
  • 1.25ns @ CL = 11 (DDR3-1600)
  • 1.5ns @ CL = 9 (DDR3-1333)
  • 1.87ns @ CL = 7 (DDR3-1066)

• ICMAX PN
• 1,024M4
• 512M8
• 256M16
• G8
• RAF
• RHF
• RKB
• RGF
• REF
• GNF
• -107
• -125
• -15E
• -187E

Standard export packaging available. Customers can choose from cartons, wooden cases, and wooden pallets according to their requirements.